Basic screen bezels

This commit is contained in:
Roberto Alsina 2022-11-24 17:45:59 -03:00
parent 8534d25e4b
commit b8d902ea11
3 changed files with 539 additions and 7 deletions

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@ -1,17 +1,12 @@
import cadquery2 as cq import cadquery2 as cq
from cadquery2 import exporters from cadquery2 import exporters
lower_stands = ( lower_stands = (
cq.Sketch() cq.Sketch().push([(0, 0), (58, 0), (58, 23), (0, 23)]).circle(3, mode="a")
.push([(0,0), (58, 0), (58, 23), (0, 23)])
.circle(3, mode="a")
) )
higher_stands = ( higher_stands = (
cq.Sketch() cq.Sketch().push([(0, 0), (58, 0), (58, 23), (0, 23)]).circle(2.65 / 2, mode="a")
.push([(0,0), (58, 0), (58, 23), (0, 23)])
.circle(2.65/2, mode="a")
) )
model = ( model = (

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import cadquery2 as cq
from cadquery2 import exporters
# Dimensions copied from modelo.py,
# TODO refactor into a separate file
# Thickness of the outer material
shell_t = 3
# Size of the kbd board
kbd_height = 98
kbd_width = 286
kbd_angle = 5
# Size of the whole object
width = kbd_width + 2 * shell_t
height = 69
thickness = 10
# Visible screen size
vis_w = 223
vis_h = 58
viewport_cutout = cq.Sketch().trapezoid(vis_w, vis_h, 90, mode="a")
# Whole screen size
scr_w = 231
scr_h = 65
scr_thickness = 5.5
screen_cutout = cq.Sketch().trapezoid(scr_w, scr_h, 90, mode="a")
# Circuit board and cable space
board_cutout = cq.Sketch().polygon(
[(0, 0), (width / 2 - 10, 0), (width / 2 - 10, vis_h), (0, vis_h), (0, 0)], mode="a"
)
model = (
cq.Workplane("XY")
.workplane()
.box(width, height, thickness)
.faces(">Z")
# Cut off viewport
.placeSketch(viewport_cutout)
.cutBlind(-1000)
# Make hole for screen assembly
.faces(">Z")
.workplane(offset=-shell_t, centerOption="CenterOfBoundBox")
# Left bezel is 4mm wider than right one, so this hole is displaced to the left
.center(-2, 0)
.placeSketch(screen_cutout)
.cutBlind(-scr_thickness)
.faces(">Z")
.workplane(offset=-shell_t-scr_thickness, centerOption="CenterOfBoundBox")
.center(0, - vis_h / 2)
.placeSketch(board_cutout)
.cutBlind(-1000)
)
exporters.export(model, "screen_mount.stl")

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vertex 1.135000e+02 -2.900000e+01 -3.500000e+00
vertex 1.135000e+02 -3.250000e+01 2.000000e+00
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outer loop
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vertex 1.135000e+02 3.250000e+01 2.000000e+00
endloop
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outer loop
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